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IC42S32200 IC42S32200L
Document Title
512K x 32 Bit x 4 Banks (64-MBIT) SDRAM
Revision History Revision No
0A 0B 0C 0D
History
Initial Draft Obselete partial refresh function Obselete 5ns speed grade Change ICC3P from 3mA to 5mA Revise typo Revise p.20,p.22 data and p.28 typo
Draft Date
September 26,2002 September 05,2003 April 27,2004 February 04,2005
Remark
The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
Integrated Circuit Solution Inc.
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IC42S32200 IC42S32200L
512K Words x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
FEATURES
* Concurrent auto precharge * Clock rate:166/143/125 MHz * Fully synchronous operation * Internal pipelined architecture * Four internal banks (512K x 32bit x 4bank) * Programmable Mode -CAS#Latency:2 or 3 -Burst Length:1,2,4,8,or full page -Burst Type:interleaved or linear burst -Burst-Read-Single-Write * Burst stop function * Individual byte controlled by DQM0-3 * Auto Refresh and Self Refresh * 4096 refresh cycles/64ms * Single +3.3V 0.3V power supply * Interface:LVTTL * Package:400 x 875 mil,86 Pin TSOP-2,0.50mm Pin Pitch and 11x13mm, 90 Ball BGA, Ball pitch 0.8mm * Pb-free package is available.
DESCRIPTION
The ICSI IC42S32200 and IC42S32200L is a high-speed CMOS configured as a quad 512K x 32 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal,CLK). Each of the 512K x 32 bit banks is organized as 2048 rows by 256 columns by 32 bits.Read and write accesses start at a selected locations in a programmed sequence. Accesses begin with the registration of a BankActive command which is then followed by a Read or Write command The ICSI IC42S32200 and IC42S32200L provides for programmable Read or Write burst lengths of 1,2,4,8,or full page, with a burst termination operation. An auto precharge function may be enable to provide a self-timed row precharge that is initiated at the end of the burst sequence.The refresh functions,either Auto or Self Refresh are easy to use. By having a programmable mode register,the system can choose the most suitable modes to maximize its performance. These devices are well suited for applications requiring high memory bandwidth.
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. (c) Copyright 2000, Integrated Circuit Solution Inc.
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IC42S32200 IC42S32200L
FUNCTIONAL BLOCK DIAGRAM
Column Decoder
Row Decoder
2048 X 256 X 32 C E L L A R R AY (BANK #0) Sense Amplifier
CLK
CLOCK BUFFER
CONTROL SIGNAL G E N E R AT O R
CKE CS# RAS# CAS# WE#
Sense Amplifier
Row Decoder Row Decoder
COMMAND DECODER MODE REGISTER
2048 X 256 X 32 C E L L A R R AY (BANK #1) Column Decoder
COLUMN COUNTER A10/AP Column Decoder
A0 A9 BS0 BS1
ADDRESS BUFFER
2048 X 256 X 32 CELL ARRAY (BANK #2) Sense Amplifier
REFRESH COUNTER
Sense Amplifier DQ BUFFER DQ0 D Q 31
Decoder Row
2048 X 256 X 32 CELL ARRAY (BANK #3)
Column Decoder
DQM0~3
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IC42S32200 IC42S32200L
PIN DESCRIPTIONS
Table 1.Pin Details of IC42S32200 and IC42S32200L Symbol Type Description
CLK CKE
Input Input
Clock:CLK is driven by the system clock.All SDRAM input signals are sampled on the positive edge of CLK.CLK also increments the internal burst counter and controls the output registers. Clock Enable:CKE activates(HIGH)and deactivates(LOW)the CLK signal.If CKE goes low synchronously with clock(set-up and hold time same as other inputs),the internal clock is suspended from the next clock cycle and the state of output and burst address is frozen as long as the CKE remains low.When all banks are in the idle state,deactivating the clock controls the entry to the Power Down and Self Refresh modes.CKE is synchronous except after the device enters Power Down and Self Refresh modes,where CKE becomes asynchronous until exiting the same mode. The input buffers,including CLK,are disabled during Power Down and Self Refresh modes,providing low standby power. Bank Select:BS0 and BS1 defines to which bank the BankActivate,Read,Write,or BankPrecharge command is being applied. Address Inputs:A0-A10 are sampled during the BankActivate command (row address A0-A10)and Read/Write command (column address A0-A7 with A10 defining Auto Precharge) to select one location out of the 256K available in the respective bank.During a Precharge command,A10 is sampled to determine if all banks are to be precharged (A10 =HIGH). The address inputs also provide the op-code during a Mode Register Set .
BS0,BS1 Input A0-A10 Input
CS#
Input
Chip Select:CS#enables (sampled LOW)and disables (sampled HIGH)the command decoder.All commands are masked when CS#is sampled HIGH.CS#provides for external bank selection on systems with multiple banks.It is considered part of the command code. Row Address Strobe:The RAS#signal defines the operation commands in conjunction with the CAS#and WE#signals and is latched at the positive edges of CLK.When RAS# and CS#are asserted "LOW"and CAS#is asserted "HIGH,"either the BankActivate command or the Precharge command is selected by the WE#signal.When the WE#is asserted "HIGH,"the BankActivate command is selected and the bank designated by BS is turned on to the active state.When the WE#is asserted "LOW,"the Precharge command is selected and the bank designated by BS is switched to the idle state after the precharge operation. Column Address Strobe:The CAS#signal defines the operation commands in conjunction with the RAS#and WE#signals and is latched at the positive edges of CLK. When RAS#is held "HIGH"and CS#is asserted "LOW,"the column access is started by asserting CAS#"LOW."Then,the Read or Write command is selected by asserting WE# "LOW"or "HIGH." Write Enable:The WE#signal defines the operation commands in conjunction with the RAS#and CAS#signals and is latched at the positive edges of CLK.The WE#input is used to select the BankActivate or Precharge command and Read or Write command. Data Input/Output Mask:DQM0-DQM3 are byte specific,nonpersistent I/O buffer controls. The I/O buffers are placed in a high-z state when DQM is sampled HIGH.Input data is masked when DQM is sampled HIGH during a write cycle.Output data is masked (two-clock latency)when DQM is sampled HIGH during a read cycle.DQM3 masks DQ31-DQ24,DQM2 masks DQ23-DQ16,DQM1 masks DQ15-DQ8,and DQM0 masks DQ7-DQ0.
RAS#
Input
CAS#
Input
WE#
Input
DQM0-3 Input
DQ0-31 Input/Output Data I/O:The DQ0-31 input and output data are synchronized with the positive edges of CLK.The I/Os are byte-maskable during Reads and Writes.
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IC42S32200 IC42S32200L
PIN FUNCTION
NC VDDQ VSSQ VDD VSS Supply Supply Supply Supply No Connect:These pins should be left unconnected. DQ Power:Provide isolated power to DQs for improved noise immunity. DQ Ground:Provide isolated ground to DQs for improved noise immunity. Power Supply:+3.3V 0.3V Ground
PIN CONFIGURATIONS 86-Pin TSOP 2
Pin Assignment (Top View)
VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC VDD DQM 0 /WE /CAS /RAS /CS NC BS0 BS1 A10/AP A0 A1 A2 DQM 2 VDD NC DQ16 VSSQ DQ17 DQ18 VDDQ DQ19 DQ20 VSSQ DQ21 DQ22 VDDQ DQ23 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 NC VSS DQM1 NC NC CL K CKE A9 A8 A7 A6 A5 A4 A3 DQM3 VSS NC DQ31 VDDQ DQ30 DQ29 VSSQ DQ28 DQ27 VDDQ DQ26 DQ25 VSSQ DQ24 VSS
90-Ball FBGA
1 A B C D E F G H J K L M N P R
DQ26 DQ28 VSSQ VSSQ VDDQ VSS A4 A7 CLK DQM1 VDDQ VSSQ VSSQ DQ11 DQ13
2
DQ24 VDDQ DQ27 DQ29 DQ31 DQM3 A5 A8 CKE NC DQ8 DQ10 DQ12 VDDQ DQ15
3
Vss VSSQ DQ25 DQ30 NC A3 A6
4
5
6
7
VDD VDDQ DQ22 DQ17 NC A2 A10
8
DQ23 VSSQ DQ20 DQ18 DQ16 DQM2 A0 BA1 CS WE DQ7 DQ5 DQ3 VSSQ DQ0
9
DQ21 DQ19 VDDQ VDDQ VSSQ VDD A1 NC RAS DQM0 VSSQ VDDQ VDDQ DQ4 DQ2
(Top View)
NC A9 NC VSS DQ9 DQ14 VSSQ VSS NC BA0 CAS VDD DQ6 DQ1 VDDQ VDD
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IC42S32200 IC42S32200L
Operation Mode
Fully synchronous operations are performed to latch the commands at the positive edges of CLK.Table 2 shows the truth table for the operation commands.
Table 2.Truth Table (Note (1),(2))
Command BankActivate BankPrecharge PrechargeAll Write Write and Auto Precharge Read Read and Autoprecharge Mode Register No-Operation Burst Stop Device Deselect AutoRefresh SelfRefresh Entry SelfRefresh Exit State Idle Any Any Active (3) Active (3) Active (3) Active (3) Set Idle Any Active(4) Any Idle Idle Idle (SelfRefresh) Clock Suspend Mode Entry Active Power Down Mode Entry Any(5) H H L L H H L L H H X X X X X X L H X X X X X X X X X X X X X X X X X X
(3)
CKEn-1 CKE H H H H H H H H H H H H H L X X X X X X X X X X X H L H
DQM(6) BS0,1 X X X X X X X X X X X X X X X X X X X X V V X V V V V
A10 L H L H L H
A9-0 X X Column address (A0 ~A7) Column address (A0 ~A7)
CS# RAS# CAS# WE# L L L L L L L L L L H L L H L X H L X H L X X L L L H H H H L H H X L L X H X X H X X H X X H H H L L L L L H H X L L X H X X H X X H X X H L L L L H H L H L X H H X H X X H X X H X X
Row address
OP code X X X X X X X X X X X X
Clock Suspend Mode Exit Active Power Down Mode Exit Any (PowerDown) Data Write/Output Enable Active Data Mask/Output Disable Active
Note: 1. V =Valid,X =Don 't care,L =Logic low,H =Logic high 2. CKEn signal is input level when commands are provided. CKEn-1 signal is input level one clock cycle before the commands are provided. 3. These are states of bank designated by BS signal. 4. Device state is 1,2,4,8,and full page burst operation. 5. Power Down Mode can not enter in the burst operation. When this command is asserted in the burst cycle,device state is clock suspend mode. 6. DQM0-3
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Commands
1 BankActivate (RAS#="L",CAS#="H",WE#="H",BS =Bank,A0-A10 =Row Address) The BankActivate command activates the idle bank designated by the BS0,1 (Bank Select) signal.By latching the row address on A0 to A10 at the time of this command,the selected row access is initiated.The read or write operation in the same bank can occur after a time delay of tRCD(min.)from the time of bank activation.A subsequent BankActivate command to a different row in the same bank can only be issued after the previous active row has been precharged (refer to the following figure).The minimum time interval between successive BankActivate commands to the same bank is defined by tRC(min.).The SDRAM has four internal banks on the same chip and shares part of the internal circuitry to reduce chip area;therefore it restricts the back-to-back activation of the four banks.tRRD(min.)specifies the minimum time required between activating different banks. After this command is used,the Write command and the Block Write command perform the no mask write operation.
T0 CLK ADDRESS Bank A Row Addr. RAS# - CAS# delay (tRCD) COMMAND Bank A Activate NOP NOP
R/W A with AutoPrecharge
T1
T2
T3 .............. Bank A Col Addr. ..............
Tn+3
Tn+4
Tn+5
Tn+6
Bank B Row Addr. RAS#- RAS# delay time (tRRD)
Bank A Row Addr.
..............
Bank B Activate
NOP
NOP
Bank A Activate
RAS# Cycle time (tRC) Auto Precharge Begin
:"H" or "L"
Bank
2
BankPrecharge command (RAS#="L",CAS#="H",WE#="L",BS =Bank,A10 ="L",A0-A9 =Don 't care) The BankPrecharge command precharges the bank disignated by BS0,1 signal.The precharged bank is switched from the active state to the idle state.This command can be asserted anytime after tRAS(min.)is satisfied from the BankActivate command in the desired bank.The maximum time any bank can be active is specified by tRAS(max.).Therefore,the precharge function must be performed in any active bank within tRAS(max.).At the end of precharge,the precharged bank is still in the idle state and is ready to be activated again.
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IC42S32200 IC42S32200L
3 PrechargeAll command (RAS#="L",CAS#="H",WE#="L",BS =Don t care,A10 ="H",A0-A9 =Don 't care) The PrechargeAll command precharges all the four banks simultaneously and can be issued even if all banks are not in the active state.All banks are then switched to the idle state. Read command (RAS#="H",CAS#="L",WE#="H",BS =Bank,A10 ="L",A0-A7 =Column Address) The Read command is used to read a burst of data on consecutive clock cycles from an active row in an active bank.The bank must be active for at least tRCD(min.)before the Read command is issued.During read bursts,the valid data-out element from the starting column address will be available following the CAS#latency after the issue of the Read command.Each subsequent data- out element will be valid by the next positive clock edge (refer to the following figure).The DQs go into high-impedance at the end of the burst unless other command is initiated.The burst length,burst sequence,and CAS#latency are determined by the mode register which is already programmed.A full-page burst will continue until terminated (at the end of the page it will wrap to column 0 and continue).
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T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK COMMAND READ A NOP NOP NOP NOP NOP NOP NOP NOP
CAS# latency=2 t CK2 , DQ s CAS# latency=3 t CK3 , DQ s
DOUT A0
DOUT A1
DOUT A2
DOUT A3
DOUT A0
DOUT A1
DOUT A2
DOUT A3
Burst Read Operation(Burst Length =4,CAS#Latency =2,3)
The read data appears on the DQs subject to the values on the DQM inputs two clocks earlier (i.e.DQM latency is two clocks for output buffers).A read burst without the auto precharge function may be interrupted by a subsequent Read or Write command to the same bank or the other active bank before the end of the burst length.It may be interrupted by a BankPrecharge/PrechargeAll command to the same bank too.The interrupt coming from the Read command can occur on any clock cycle following a previous Read command (refer to the following figure).
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK COMMAND READ A READ B NOP NOP NOP NOP NOP NOP NOP
CAS# latency=2 t CK2 , DQ s CAS# latency=3 t CK3 , DQ s
DOUT A0
DOUT B0
DOUT B1
DOUT B2
DOUT B3
DOUT A 0
DOUT B0
DOUT B1
DOUT B2
DOUT B3
Read Interrupted by a Read (Burst Length =4,CAS#Latency =2,3)
The DQM inputs are used to avoid I/O contention on the DQ pins when the interrupt comes from a Write command.The DQMs must be asserted (HIGH)at least two clocks prior to the Write command to suppress data-out on the DQ pins.To guarantee the DQ pins against I/O contention,a single cycle with high-impedance on the DQ pins must occur between the last read data and the Write command (refer to the following three figures).If the data output of the burst read occurs at the second clock of the burst write,the DQMs must be asserted (HIGH)at least one clock prior to the Write command to avoid internal bus contention.
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IC42S32200 IC42S32200L
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
DQM
COMMAND
NOP
READ A
NOP
NOP
NOP
NOP
WRITE B
NOP
NOP
DQ's
DOUT A
Must be Hi-Z before the Write Command
DINB 0
DINB 1
DINB 2
: "H" or "L"
Read to Write Interval (Burst Length = 4,CAS#Latency =3)
T0
CLK DQM
T1
T2
T3
T4
T5
T6
T7
T8
1 Clk Interval
COMMAND
NOP
NOP
BANKA ACTIVAT E
NOP
READ A
WRITEA
NOP
NOP
NOP
CAS# latency=2 tCK2, DQs
: "H" or "L"
DIN A0
DIN A1
DIN A2
DIN A3
Read to Write Interval (Burst Length = 4,CAS#Latency =2)
T0 CLK
DQM
T1
T2
T3
T4
T5
T6
T7
T8
COMMAND CAS# latency=2 t CK2 ,tCK2, DQs DQ's
NOP
NOP
READ A
NOP
NOP
WRITEB
NOP
NOP
NOP
DIN B0
DIN B1
DIN B2
DIN B3
: "H" or "L"
Read to Write Interval (Burst Length = 4,CAS#Latency =2)
A read burst without the auto precharge function may be interrupted by a BankPrecharge/ PrechargeAll command to the same bank.The following figure shows the optimum time that BankPrecharge/PrechargeAll command is issued in different CAS#latency. 10 Integrated Circuit Solution Inc.
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T0
CLK Bank, Col A
T1
T2
T3
T4
T5
T6
T7
T8
ADDRESS
Bank(s )
Bank, Row
tRP
COMMAND
READ A NOP NOP NOP Precharge NOP NOP Activate NOP
CAS# latency=2 t CK2 , DQ s CAS# latency=3 t CK3 , DQ s
DOUT A 0
DOUT A 1
DOUT A 2
DOUT A 3
DOUT A 0
DOUT A 1
DOUT A 2
DOUT A 3
Read to Precharge (CAS#Latency =2,3)
5 Write command (RAS#="H",CAS#="L",WE#="L",BS =Bank,A10 ="L",A0-A7 =Column Address) The Write command is used to write a burst of data on consecutive clock cycles from an active row in an active bank.The bank must be active for at least tRCD(min.)before the Write command is issued.During write bursts, the first valid data-in element will be registered coincident with the Write command.Subsequent data elements will be registered on each successive positive clock edge (refer to the following figure).The DQs remain with highimpedance at the end of the burst unless another command is initiated.The burst length and burst sequence are determined by the mode register,which is already programmed.A full-page burst will continue until terminated (at the end of the page it will wrap to column 0 and continue).
T0 CLK COMMAND
NOP
T1
T2
T3
T4
T5
T6
T7
T8
WRITEA I
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DQ0 - DQ3
DIN A 0
DIN A1
DIN A 2
DIN A 3
don't care
The first data element and the write are registered on the same clock edge.
Extra data is masked.
Burst Write Operation (Burst Length =4,CAS#Latency =2,3)
A write burst without the AutoPrecharge function may be interrupted by a subsequent Write, BankPrecharge/ PrechargeAll,or Read command before the end of the burst length.An interrupt coming from Write command can occur on any clock cycle following the previous Write command (refer to the following figure).
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IC42S32200 IC42S32200L
T0
CLK COMMAND NOP
T1
T2
T3
T4
T5
T6
T7
T8
WRITEA
WRITEB
NOP
NOP
NOP
NOP
NOP
NOP
1 Clk Interval DQ's DIN A0 DIN B0 DIN B1 DIN B2 DIN B3
Write Interrupted by a Write (Burst Length =4,CAS#Latency =2,3)
The Read command that interrupts a write burst without auto precharge function should be issued one cycle after the clock edge in which the last data-in element is registered.In order to avoid data contention,input data must be removed from the DQs at least one clock cycle before the first read data appears on the outputs (refer to the following figure).Once the Read command is registered,the data inputs will be ignored and writes will not be executed.
T0 CLK COMMAND NOP WRITEA READ B NOP NOP NOP NOP NOP NOP T1 T2 T3 T4 T5 T6 T7 T8
CAS# latency=2 t CK2 , DQ's CAS# latency=3 t CK3 , DQ's
DIN A0
don't care
DOUT B0
DOUT B1
DOUT B2
DOUT B3
DIN A0
don't care
don't care
DOUT B0
DOUT B1
DOUT B2
DOUT B3
Input data for the write is masked.
DI N
Input data must be removed from the DQs at least one clock cycle before the Read data appears on the outputs to avoid data contention.
Write Interrupted by a Read (Burst Length =4,CAS#Latency =2,3)
The BankPrecharge/PrechargeAll command that interrupts a write burst without the auto precharge function should be issued m cycles after the clock edge in which the last data-in element is registered,where m equals tWR/ tCK rounded up to the next whole number.In addition,the DQM signals must be used to mask input data,starting with the clock edge following the last data-in element and ending with the clock edge on which the BankPrecharge/ PrechargeAll command is entered (refer to the following figure).
T0 CLK T1 T2 T3 T4 T5 T6
DQM t RP COMMAND WRITE NOP Precharge NOP NOP Activate NOP
ADDRESS
BANK COL n t WR DIN n
BANK (S)
ROW
DQ
n+1
: don t care
Note:The DQMs can remain low in this example if the length of the write burst is 1 or 2.
Write to Precharge
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6 Concurrent Auto Precharge An access command (READ or WRITE) to another bank while an access command with auto precharge enabled is executing is not allowed by SDRAMs, unless the SDRAM supports CONCURRENT AUTO PRECHARGE. ICSI SDRAMs support CONCURRENT AUTO PRECHARGE. Four cases where CONCURRENT AUTO PRECHARGE occurs are defined below. READ with Auto Precharge * Interrupted by a READ (with or without auto precharge): A READ to bank m will interrupt a READ on bank n, CAS latency later. The PRECHARGE to bank n will begin when the READ to bank m is regis-tered.
READ With Auto Precharge Interrupted by a READ
T0 CLK
READ - AP BANK n READ - AP BANK m
T1
T2
T3
T4
T5
T6
T7
COMMAND BANK n
NOP
NOP
NOP
NOP
NOP
NOP
Page Active
READ with Burst of 4
Interrupt Burst, Precharge t RP - BANK n
Idle t RP - BANK m Precharge
Internal States
BANK m
Page Active
READ with Burst of 4
ADDRESS DQ
BANK n, COL a
BANK m, COL d DOUT a DOUT a+1 DOUT d DOUT d+1
CAS Latency = 3 (BANK n)
NOTE: DQM is LOW.
CAS Latency = 3 (BANK m)
DON T CARE
* Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will interrupt a READ on bank n when registered. DQM should be used two clocks prior to the WRITE command to prevent bus contention. The PRECHARGE to bank n will begin when the WRITE to bank m is registered.
READ With Auto Precharge Interrupted by a WRITE
T0 CLK
READ - AP BANK n Page Active WRITE - AP BANK m
T1
T2
T3
T4
T5
T6
T7
COMMAND BANK n
NOP
NOP
NOP
NOP
NOP
NOP
READ with Burst of 4
Interrupt Burst, Precharge t RP - BANK n
Idle t WR - BANK m Write-Back
Internal States
BANK m
BANK n, COL a
Page Active
WRITE with Burst of 4
ADDRESS DQM 1
BANK m, COL d
DQ
CAS Latency = 3 (BANK n)
DOUT a
DIN d
DIN d+1
DIN d+2
DIN d+3
NOTE: 1. DQM is HIGH at T2 to prevent D
OUT-a+1
from contending with D
IN-d
at T4. DON'T CARE
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IC42S32200 IC42S32200L
WRITE with Auto Precharge * Interrupted by a READ (with or without auto precharge): A READ to bank m will interrupt a WRITE on bank n when registered, with the data-out ap- pearing CAS latency later. The PRECHARGE to bank n will begin after t WR is met, where t WR begins when the READ to bank m is registered. The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m.
WRITE With Auto Precharge Interrupted by a READ
T0 CLK
WRITE - AP BANK n READ - AP BANK m
T1
T2
T3
T4
T5
T6
T7
COMMAND BANK n
NOP
NOP
NOP
NOP
NOP
NOP
Page Active
WRITE with Burst of 4
Interrupt Burst, Write-Back t WR - BANK n
Precharge t RP - BANK n t RP - BANK m
Internal States
BANK m
Page Active
READ with Burst of 4
ADDRESS
BANK n, COL a DIN a DIN a+1
BANK m, COL d DOUT d CAS Latency = 3 (BANK m) DOUT d+1
DQ
NOTE: 1. DQM is LOW.
DON'T CARE
* Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will interrupt a WRITE on bank n when registered. The PRECHARGE to bank n will begin after t WR is met, where t WR begins when the WRITE to bank m is registered. The last valid data WRITE to bank n will be data registered one clock prior to a WRITE to bank m.
WRITE With Auto Precharge Interrupted by a WRITE
T0 T1 T2 T3 T4 T5 T6 T7
COMMAND BANK n
NOP
WRITE - AP BANK n
NOP
WRITE - AP BANK m
NOP
NOP
NOP
Page Active
WRITE with Burst of 4
Interrupt Burst, Write-Back t WR - BANK n
Precharge t RP - BANK n t WR - BANK m Write-Back
Internal States
BANK m
Page Active
WRITE with Burst of 4
ADDRESS
BANK n, COL a
DIN a
BANK m, COL d DIN a+1 DIN a+2 DIN d DIN d+1
DIN d+2 DIN d+3
NOTE: 1. DQM is LOW.
DON'T CARE
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7 Mode Register Set command (RAS#="L",CAS#="L",WE#="L",BS0,1 and A10-A0 =Register Data) The mode register stores the data for controlling the various operating modes of SDRAM.The Mode Register Set command programs the values of CAS#latency,Addressing Mode and Burst Length in the Mode register to make SDRAM useful for a variety of different applications.The default values of the Mode Register after powerup are undefined;therefore this command must be issued at the power-up sequence.The state of pins BS0,1 and A10~A0 in the same cycle is the data written to the mode register.One clock cycle is required to complete the write in the mode register (refer to the following figure).The contents of the mode register can be changed using the same command and the clock cycle requirements during operation as long as all banks are in the idle state.
Integrated Circuit Solution Inc.
DR036-0D 02/04/2005
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IC42S32200 IC42S32200L
T0 CLK tCK2 CKE Clock min. CS# T1 T2 T3 T4 T5 T6 T7 T8 T9 T10
RAS#
CAS#
WE# Address Key ADDR. DQM Hi-Z
tRP
DQ
Precharge All
Mode Register Set Command
Any Command
Mode Register Set Cycle
The mode register is divided into various fields depending on functionality.
Address BS0,1 A10/AP Function RFU* RFU* A9 WBL A8 A7 A6 A5 A4 A3 BT A2 A1 A0
Test Mode
CAS Latency
Burst Length
*Note:RFU (Reserved for future use)should stay 0 during MRS cycle.
*
Burst Length Field (A2~A0) This field specifies the data length of column access using the A2~A0 pins and selects the Burst Length to be 2, 4,8,or full page. A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 Burst Length 1 2 4 8 Reserved Reserved Reserved Full Page Integrated Circuit Solution Inc.
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IC42S32200 IC42S32200L
* Burst Type Field (A3) The Burst Type can be one of two modes,Interleave Mode or Sequential Mode. A3 0 1 Burst Type Sequential Interleave
--Addressing Sequence of Sequential Mode An internal column address is performed by increasing the address from the column address which is input to the device.The internal column address is varied by the Burst Length as shown in the following table.When the value of column address,(n +m),in the table is larger than 255,only the least significant 8 bits are effective.
Data n Column Address 0
n
1
n+1
2
n+2
3
n+3
4
n+4
5
n+5
6
n+6
7
n+7
-
255
n+255
256
n
257
n+1
-
2 words: Burst Length 4 words: 8 words: Full Page: Column address is repeated until terminated.
* Addressing Sequence of Interleave Mode A column access is started in the input column address and is performed by inverting the address bits in the sequence shown in the following table.
Data n Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 A7 A7 A7 A7 A7 A7 A7 A7 A6 A6 A6 A6 A6 A6 A6 A6 A5 A5 A5 A5 A5 A5 A5 A5 Column Address A4 A4 A4 A4 A4 A4 A4 A4 A3 A3 A3 A3 A3 A3 A3 A3 A2 A2 A2 A2 A2# A2# A2# A2# A1 A1 A1# A1# A1 A1 A1# A1# A0 A0# A0 A0# A0 A0# A0 A0# Burst Length 4 words 8 words
* CAS#Latency Field (A6~A4) This field specifies the number of clock cycles from the assertion of the Read command to the first read data.The minimum whole value of CAS#Latency depends on the frequency of CLK.The minimum whole value satisfying the following formula must be programmed into this field. tCAC(min)<=CAS#Latency X tCK A6 0 0 0 0 1 A5 0 0 1 1 X A4 0 1 0 1 X CAS#Latency Reserved Reserved 2 clocks 3 clocks Reserved
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IC42S32200 IC42S32200L
* Test Mode field (A8~A7) These two bits are used to enter the test mode and must be programmed to "00"in normal operation. A8 0 0 1 A7 0 1 X Test Mode normal mode Vendor Use Only Vendor Use Only
* Write Burst Length (A9) This bit is used to select the burst write length. A9 0 1 8 Write Burst Length Burst Single Bit
9
No-Operation command (RAS#="H",CAS#="H",WE#="H") The No-Operation command is used to perform a NOP to the SDRAM which is selected (CS# is Low).This prevents unwanted commands from being registered during idle or wait states. Burst Stop command (RAS#="H",CAS#="H",WE#="L") The Burst Stop command is used to terminate either fixed-length or full-page bursts.This command is only effective in a read/write burst without the auto precharge function.The terminated read burst ends after a delay equal to the CAS#latency (refer to the following figure).The termination of a write burst is shown in the following figure.
T0 CLK COMMAND READ A NOP NOP NOP Burst Stop NOP NOP NOP NOP T1 T2 T3 T4 T5 T6 T7 T8
The Burst ends after a delay equal to the CAS# latency. CAS# latency=2 tCK2,DQ's CAS# latency=3 tCK3,DQ's DOUT A0 DOUT A1 DOUT A2 DOUT A3
DOUT A0
DOUT A1
DOUT A2
DOUT A3
Termination of a Burst Read Operation (Burst Length > 4,CAS#Latency =2,3)
T0 CL K COMMAN D NOP WRITE A NOP NOP Burst Stop NOP NOP NOP NOP T1 T2 T3 T4 T5 T6 T7 T8
CAS# latency=2,3 DQ's
DIN A0
DIN A1
DIN A2
don't care
Input Data for the Write is masked.
Termination of a Burst Write Operation (Burst Length =X)
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Integrated Circuit Solution Inc.
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IC42S32200 IC42S32200L
10 Device Deselect command (CS#="H") The Device Deselect command disables the command decoder so that the RAS#,CAS#,WE# and Address inputs are ignored,regardless of whether the CLK is enabled.This command is similar to the No Operation command. AutoRefresh command (RAS#="L",CAS#="L",WE#="H",CKE ="H",BS0,1 =Don t care,A0-A10 =Don 't care) The AutoRefresh command is used during normal operation of the SDRAM and is analogous to CAS#-beforeRAS#(CBR)Refresh in conventional DRAMs.This command is non-persistent,so it must be issued each time a refresh is required.The addressing is generated by the internal refresh controller.This makes the address bits a "don 't care"during an AutoRefresh command.The internal refresh counter increments automatically on every auto refresh cycle to all of the rows.The refresh operation must be performed 4096 times within 64ms.The time required to complete the auto refresh operation is specified by tRC(min.).To provide the AutoRefresh command, all banks need to be in the idle state and the device must not be in power down mode (CKE is high in the previous cycle).This command must be followed by NOPs until the auto refresh operation is completed.The precharge time requirement,tRP(min),must be met before successive auto refresh operations are performed. SelfRefresh Entry command (RAS#="L",CAS#="L",WE#="H",CKE ="L",A0-A10 =Don 't care) The SelfRefresh is another refresh mode available in the SDRAM.It is the preferred refresh mode for data retention and low power operation.Once the SelfRefresh command is registered,all the inputs to the SDRAM become "don 't care"with the exception of CKE,which must remain LOW.The refresh addressing and timing is internally generated to reduce power consumption.The SDRAM may remain in SelfRefresh mode for an indefinite period. The SelfRefresh mode is exited by restarting the external clock and then asserting HIGH on CKE (SelfRefresh Exit command). SelfRefresh Exit command (CKE ="H",CS#="H"or CKE ="H",RAS#="H",CAS#="H",WE#="H") This command is used to exit from the SelfRefresh mode.Once this command is registered, NOP or Device Deselect commands must be issued for tRC(min.)because time is required for the completion of any bank currently being internally refreshed.If auto refresh cycles in bursts are performed during normal operation,a burst of 4096 auto refresh cycles should be completed just prior to entering and just after exiting the SelfRefresh mode. Clock Suspend Mode Entry /PowerDown Mode Entry command (CKE ="L") When the SDRAM is operating the burst cycle,the internal CLK is suspended(masked)from the subsequent cycle by issuing this command (asserting CKE "LOW").The device operation is held intact while CLK is suspended.On the other hand,when all banks are in the idle state,this command performs entry into the PowerDown mode.All input and output buffers (except the CKE buffer)are turned off in the PowerDown mode.The device may not remain in the Clock Suspend or PowerDown state longer than the refresh period (64ms)since the command does not perform any refresh operations. Clock Suspend Mode Exit /PowerDown Mode Exit command When the internal CLK has been suspended,the operation of the internal CLK is einitiated from the subsequent cycle by providing this command (asserting CKE "HIGH").When the device is in the PowerDown mode,the device exits this mode and all disabled buffers are turned on to the active state.tPDE(min.)is required when the device exits from the PowerDown mode.Any subsequent commands can be issued after one clock cycle from the end of this command. Data Write /Output Enable,Data Mask /Output Disable command (DQM ="L","H") During a write cycle,the DQM signal functions as a Data Mask and can control every word of the input data.During a read cycle,the DQM functions as the controller of output buffers.DQM is also used for device selection,byte selection and bus control in a memory system. 19
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12
13
14
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Absolute Maximum Rating
Symbol VIN,VOUT VDD,VDDQ TOPR TSTG TSOLDER PD IOUT Item Input,Output Voltage Power Supply Operating Temperature Storage Temperature Soldering Temperature (10s) Power Dissipation Short Circuit Output Current Rating -0.3~VDD +0.3 -0.3~4.6 0~70 -55~150 260 1 50 Unit V V C C C W mA Note 1 1 1 1 1 1 1
Recommended D.C.Operating Conditions (Ta =0~70 C)
Symbol VDD VDDQ VIH VIL Parameter Power Supply Voltage Power Supply Voltage(for I/O Buffer) LVTTL Input High Voltage LVTTL Input Low Voltage Min. 3.0 3.0 2.0 -1.2 Typ. 3.3 3.3 Max. 3.6 3.6 VDDQ +1.2 0.8 Unit V V V V Note 2 2 2 2
Capacitance (VDD =3.3V,f =1MHz,Ta =25 C)
Symbol CI CI/O Parameter Input Capacitance Input/Output Capacitance Min. Max. 4.5 6.5 Unit pF pF
Note: 1. These parameters are periodically sampled and are not 100% tested. 2. VIH(max) for pulse width with 3ns of duration VIL(min) for pulse width with 3ns of duration
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Integrated Circuit Solution Inc.
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IC42S32200 IC42S32200L
Recommended D.C.Operating Conditions (VDD =3.3V 0.3V,Ta =0~70 C)
Description/Test condition Operating Current 1 bank tRC tRC(min), Outputs Open, Input operation signal one transition per one cycle Precharge Standby Current in power down mode tCK = 15ns, CKE VIL(max) Precharge Standby Current in power down mode tCK = , CKE VIL(max) Precharge Standby Current in non-power down mode tCK = 15ns, CS# VIH(min), CKE VIH nput signals are changed once during 30ns. Precharge Standby Current in non-power down mode tCK = , CLK VIL(max), CKE VIH Active Standby Current in power down mode C KE VIL(max), tCK = 15ns Active Standby Current in power down mode CKE& CLK VIL(max), tCK = Active Standby Current in non-power down mode CKE VIH(min), CS# VIH(min), tCK = 15ns Active Standby Current in non-power down mode CKE VIH(min), CLK VIL(max), tCK = Operating Current (Burst mode) tCK =tCK(min), Outputs Open, Multi-bank interleave Refresh Current tRC TrC(min) Self Refresh Current C KE 0.2V Symbol ICC1 ICC2P ICC2PS ICC2N ICC2NS ICC3P ICC3PS ICC3N ICC3NS ICC4 ICC5 ICC6
- 6/7/8 Max.
Unit
Note
140/130/130 2 2 20 10 5 5 30 20 200/180/150 200/180/160 0.4 (L-Version) 1 mA
3 3
3
3 3
3, 4 3
Parameter IIL VOH VOL
Description Input Leakage Current (0V VIN VDD, All other pins not under test = 0V ) LVTTL Output "H" Level Voltage ( IOUT = -2mA ) LVTTL Output "L" Level Voltage ( IOUT = 2mA )
Min. -5 2.4
Max. +5
Unit A V
Note
0.4
V
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IC42S32200 IC42S32200L
Electrical Characteristics and Recommended A.C.Operating Conditions (VDD =3.3V 0.3V,Ta =0~70 C)(Note:5,6,7,8)
- 6/7/8 Symbol A.C. Parameter Min. Max. Unit Note
tRC tRRD tRCD tRP tRAS tCK2 tCK3 tAC2 tAC3 tOH tCH tCL tIS tIH tLZ tHZ tDAL tSRX tRFC tREF tWR tCCD tMRS tPDE
Row cycle time (same bank) Row activate to row activate delay (different banks) RAS# to CAS# delay (same bank) Precharge to refresh/row activate command (same bank) Row activate to precharge time (same bank) Clock cycle time CL* = 2 CL* = 3 Access time from CLK (positive edge) Data output hold time Clock high time Clock low time Data/Address/Control Input set-up time Data/Address/Control Input hold time Data output low impedance Data output high impedance Input data to active/refresh command delay time (During Auto-precharge) Exit self refresh and active command Auto refresh Period Refresh cycle time(4096) Write Recovery Time CAS# to CAS# Delay time Mode Register Set cycle time CKE to clock enable or power down exit setup mode CL* = 2 CL* = 3
60/70/80 12/14/16 18/21/24 18/21/24 42/49/56 - / - /10 6/7/8 - / - /8 5.5/5.5/6 2/2.5/2.5 2/3/3 2/3/3 1.5/1.75/2 1 1 5.5/5.5/6 2CLK+tRP 70 60/70/80 64 2 1 2 1 CLK ms ns 100,000
9 9 9 9 9
9 9 10 10 10 10 9 8
* CL is CAS# Latency.
Note: 1. Stress greater than those listed under "Absolute Maximum Ratings"may cause permanent damage to the device. 2. All voltages are referenced to VSS. 3. These parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum value of tCK and tRC.Input signals are changed one time during tCK. 4. These parameters depend on the output loading.Specified values are obtained with the output open. 5. Power-up sequence is described in Note 11.
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6.A.C.Test Conditions
LVTTL Interface
Reference Level of Output Signals Output Load Input Signal Levels Transition Time (Rise and Fall)of Input Signals Reference Level of Input Signals
3.3V 1.2k Output 30pF 870
1.4V /1.4V Reference to the Under Output Load (B) 2.4V /0.4V 1ns 1.4V
1.4V 50 Output
Z0=50
30pF
LVTTL D.C. Test Load (A)
LVTTL A.C. Test Load (B)
Transition times are measured between VIH and VIL.Transition(rise and fall)of input signals are in a fixed slope (1 ns). 8. tHZ defines the time in which the outputs achieve the open circuit condition and are not at reference levels. 9. If clock rising time is longer than 1 ns,(tR /2 -0.5)ns should be added to the parameter. 10. Assumed input rise and fall time tT (tR &tF )=1 ns If tR or tF is longer than 1 ns,transient time compensation should be considered,i.e.,[(tr +tf)/2 -1 ]ns should be added to the parameter. 11. Power up Sequence Power up must be performed in the following sequence. 1) Power must be applied to VDD and VDDQ(simultaneously)when all input signals are held "NOP"state and both CKE ="H"and DQM ="H."The CLK signals must be started at the same time. 2) After power-up,a pause of 200 seconds minimum is required.Then,it is recommended that DQM is held "HIGH"(VDD levels)to ensure DQ output is in high impedance. 3) All banks must be precharged. 4) A minimum of 2 Auto-Refresh dummy cycles must be required to stabilize the internal circuitry of the device. 5) Mode Register Set command must be asserted to initialize the Mode register.
7.
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IC42S32200 IC42S32200L
Timing Waveforms
Figure 1.AC Parameters for Write Timing (Burst Length=4,CAS#Latency=2)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK
tCH
CKE
tCL tIS tIS tIH
tCK2
Begin Auto Precharge Bank A Begin Auto Precharge Bank B
tIS
CS#
RAS#
CAS#
WE#
-5 ,
, -7 ,
x
x
BS0,1
tIS
ADDR.
RBx
tIH
CAx RBx CBx RAy CAy RAz RBy
DQM
tRCD
Hi-Z
tRC
Ax0 Ax1 Ax2
tDAL
Ax3 Bx0 Bx1 Bx2
tIS
Bx3 Ay0
tIH
Ay1 Ay2 Ay3
tWR tRP
tRRD
DQ
Activate Write with Activate Write with Activate Command Auto Precharge Command Auto Precharge Command Bank A Command Bank B Command Bank A Bank A Bank B
Write Command Bank A
Precharge Activate Command Command Bank A Bank A
Activate Command Bank B
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Integrated Circuit Solution Inc.
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IC42S32200 IC42S32200L
Figure 2.AC Parameters for Read Timing (Burst Length=2,CAS#Latency=2)
T0 CLK
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
tCH tCL
CKE
tCK2 tIS
Begin AutoPrecharge Bank B
tIS
CS# RAS#
tIH
tIH
CAS#
WE#
BS0,1
tIH
A10
RAx RBx RAy
tIS
A0-A9
RAx CAx RBx CBx RAy
tRRD
DQM Hi-Z DQ
tRAS tRC tAC2 tLZ tAC2
Ax0
tRCD
tHZ
Ax1 Bx0
tRP
Bx1
tOH
Activate Command Bank A Read Command Bank A Activate Command Bank B Read with Auto Precharge Command Bank B Precharge Command Bank A
tHZ
Activate Command Bank A
Integrated Circuit Solution Inc.
DR036-0D 02/04/2005
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IC42S32200 IC42S32200L
Figure 3.Auto Refresh (CBR)(Burst Length=4,CAS#Latency=2)
T0 CLK
T1
T2
T3
T4
T5
T6
T7
T8
T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
tCK2
CKE
CS#
RAS#
CAS#
WE#
BS0,1
A10
RAx
A0-A9
RAx
CAx
DQM
tRP
tRC
tRC
DQ
Read Command Bank A
Ax0
Ax1
Ax2
Ax3
Precharge All Auto Refresh Command Command
Auto Refresh Command
Activate Command Bank A
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Integrated Circuit Solution Inc.
DR036-0D 02/04/2005
IC42S32200 IC42S32200L
Figure 4.Power on Sequene and Auto Refresh (CBR)
T0 T1 T2 T3 T4 T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK CKE
High level is required
Minimum of 2 Refresh Cycles are required
tMRS
CS
RAS
CAS
WE
BS0, 1
A10
Address Key
ADD
DQM
High Level is Necessary
tRP
DQ
Hi-Z
tRC
Precharge Inputs Command All Banks must be stable for 200us
1st Auto Refresh Command
2nd Auto Refresh Command
Mode Register Set Command
Command
Integrated Circuit Solution Inc.
DR036-0D 02/04/2005
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IC42S32200 IC42S32200L
Figure 5.Self Refresh Entry &Exit Cycle
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
CLK
*Note 1
*Note 2 *Note 4 *Note 3
tRC(min) tSRX
*Note 7
CKE
tPDE
*Note 5 *Note 6
tIS
CS#
RAS#
*Note 8 *Note 8
CAS#
BS0,1
A0-A9 WE#
DQM
DQ
Hi-Z
Hi-Z
SelfRefresh Enter
SelfRefresh Exit
Auto Refresh
Note:To Enter SelfRefresh Mode 1. CS#,RAS#&CAS#with CKE should be low at the same clock cycle. 2. After 1 clock cycle,all the inputs including the system clock can be don 't care except for CKE. 3. The device remains in SelfRefresh mode as long as CKE stays "low". Once the device enters SelfRefresh mode,minimum tRAS is required before exit from SelfRefresh. To Exit SelfRefresh Mode 4. System clock restart and be stable before returning CKE high. 5. Enable CKE and CKE should be set high for minimum time of tSRX. 6. CS#starts from high. 7. Minimum tRC is required after CKE going high to complete SelfRefresh exit. 8. 2048 cycles of burst AutoRefresh is required before SelfRefresh entry and after SelfRefresh exit if the system uses burst refresh.
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Integrated Circuit Solution Inc.
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Figure 6.2.Clock Suspension During Burst Read (Using CKE) (Burst Length=4,CAS#Latency=2)
T0
CLK
T 1 T2
T3
T4
T5
T6
T7
T8
T9
T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
tCK2
CKE
CS#
RAS#
CAS#
WE#
BS0,1 A10
RAx
A0-A9
RAx
CAx
DQM
tHZ
DQ Hi-Z
Ax0 Ax1 Ax2 Ax3
Activate Command Bank A
Read Command Bank A
Clock Suspend 1 Cycle
Clock Suspend 2 Cycle
Clock Suspend 3 Cycle
Note:CKE to CLK disable/enable =1 clock
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DR036-0D 02/04/2005
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IC42S32200 IC42S32200L
Figure 6.3.Clock Suspension During Burst Read (Using CKE) (Burst Length=4,CAS#Latency=3)
T0 T 1 T 2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK3
CKE
CS#
RAS#
CAS#
WE#
BS0,1
A10
RAx
A0-A9
RAx
CAx
DQM
tHZ
DQ Hi-Z
Ax0 Ax1 Ax2 Ax3
Activate Command Bank A
Read Command Bank A
Clock Suspend Clock Suspend 1 Cycle 2 Cycle
Clock Suspend 3 Cycle
Note:CKE to CLK disable/enable =1 clock
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IC42S32200 IC42S32200L
Figure 7.2.Clock Suspension During Burst Write (Using CKE) (Burst Length=4,CAS#Latency=2)
T0
CLK
T 1 T2
T3
T4
T5
T6
T7
T8
T9
T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
tCK2
CKE
CS#
RAS#
CAS#
WE#
BS0,1
A10
RAx
A0-A9
RAx
CAx
DQM
DQ
Hi-Z
DAx0
DAx1
DAx2
DAx3
Activate Command Bank A
Clock Suspend Clock Suspend 1 Cycle 2 Cycle
Clock Suspend 3 Cycle
Write Command Bank A
Note:CKE to CLK disable/enable =1 clock
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IC42S32200 IC42S32200L
Figure 7.3.Clock Suspension During Burst Write (Using CKE) (Burst Length=4,CAS#Latency=3)
T0
CLK CKE
T 1 T2
T3 T4
T5 T6
T7 T8
T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
tCK3
CS#
RAS#
CAS#
WE#
BS0,1
A10
RAx
A0-A9
RAx
CAx
DQM
DQ Hi-Z
DAx0
DAx1
DAx2
DAx3
Activate Command Bank A
Clock Suspend Clock Suspend 2 Cycle 1 Cycle
Clock Suspend 3 Cycle
Write Command Bank A
Note:CKE to CLK disable/enable =1 clock
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Figure 8.Power Down Mode and Clock Mask (Burst Lenght=4, CAS#Latency=2)
T0
CLK
T 1 T2
T3
T4
T5
T6
T7
T8
T9
T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
tCK2
CKE
tIS
tPDE
Valid
CS#
RAS#
CAS#
WE#
BS0,1
A10
RAx
A0-A9
RAx
CAx
DQM
tHZ
Hi-Z
DQ
ACTIVE STANDBY Read Activate Command Command Bank A Bank A Power Down Power Down Mode Exit Mode Entry Ax0 Ax1 Ax2 Ax3 PRECHARGE STANDBY
Clock Mask Start
Clock Mask End
Precharge Command Bank A Power Down Mode Entry
Power Down Mode Exit Any Command
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IC42S32200 IC42S32200L
Figure 9.2.Random Column Read (Page within same Bank) (Burst Length=4,CAS#Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
CKE
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAw
RAz
A0-A9
RAw
CAw
CAx
CAy
RAz
CAz
DQM
DQ
Hi-Z
Aw0
Aw1 Aw2
Aw3 Ax0
Ax1
Ay0
Ay1
Ay2
Ay3
Az0
Az1
Az2
Az3
Activate Command Bank A
Read Command Bank A
Read Command Bank A
Read Command Bank A
Precharge Activate Command Command Bank A Bank A
Read Command Bank A
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Figure 9.3.Random Column Read (Page within same Bank) (Burst Length=4,CAS#Latency=3)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK3
CKE
CS#
RAS#
CAS#
WE#
BS0,1
A10
RAw
RAz
A0-A9
RAw
CAw
CAx
CAy
RAz
CAz
DQM
DQ
Hi-Z
Aw0 Aw1 Aw2
Aw3
Ax0
Ax1
Ay0
Ay1
Ay2
Ay3
Az0
Activate Command Bank A
Read Command Bank A
Read Command Bank A
Read Command Bank A
Precharge Command Bank A
Activate Command Bank A
Read Command Bank A
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IC42S32200 IC42S32200L
Figure 10.2.Random Column Write (Page within same Bank) (Burst Length=4,CAS#Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
CKE
CS#
RAS#
CAS#
WE#
BS0,1
A10
RBw
RBz
A0-A9
RBw
CBw
CBx
CBy
RBz
CBz
DQM
DQ
Hi-Z
DBw0 DBw1 DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3
DBz0 DBz1 DBz2 DBz3
Activate Command Bank A
Write Command Bank A
Write Command Bank B
Write Command Bank B
Precharge Command Bank B
Activate Command Bank B
Write Command Bank B
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Integrated Circuit Solution Inc.
DR036-0D 02/04/2005
IC42S32200 IC42S32200L
Figure 10.3.Random Column Write (Page within same Bank) (Burst Length=4,CAS#Latency=3)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK3
CKE
CS#
RAS#
CAS#
WE#
BS0,1
A10
RBw
RBz
A0-A9
RBw
CBw
CBx
CBy
RBz
CBz
DQM
Hi-Z DQ
DBw0 DBw1 DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3
DBz0 DBz1 DBz2
Activate Command Bank A
Write Command Bank A
Write Command Bank B
Write Command Bank B
Precharge Command Bank B
Activate Command Bank B
Write Command Bank B
Integrated Circuit Solution Inc.
DR036-0D 02/04/2005
37
IC42S32200 IC42S32200L
Figure 11.3.Random Row Read (Interleaving Banks) (Burst Length=8,CAS#Latency=3)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK3
CKE High
CS#
RAS#
CAS#
WE#
BS0,1
A10
RBx
RAx
RBy
A0-A9
RBx
CBx
RAx
CAx
RBy
CBy
tRCD
DQM
tAC3
tRP
DQ
Hi-Z
Bx0
Bx1 Bx2
Bx3
Bx4
Bx5
Bx6
Bx7
Ax0
Ax1
Ax2
Ax3
Ax4
Ax5
Ax6
Ax7
By0
Activate Command Bank B
Read Command Bank B
Activate Command Bank A
Read Command Bank A
Precharge Command Bank B
Activate Command Bank B
Read Command Bank B
Precharge Command Bank A
38
Integrated Circuit Solution Inc.
DR036-0D 02/04/2005
IC42S32200 IC42S32200L
Figure 12.1.Random Row Write (Interleaving Banks) (Burst Length=8,CAS#Latency=1)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK
tCK1
CKE High
CS#
RAS#
CAS#
WE#
BS0,1
A10
RAx
RBx
RAy
A0-A9
RAx
CAx
RBx CBx
RAy
CAy
tRCD
DQM
Hi-Z
tRP
tWR
DQ
DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 DBx3 DBx4 DBx5 DBx6 DBx7
DAy0 DAy1 DAy2 DAy3
Activate Command Bank A
Write Command Bank A
Activate Command Bank B Write Command Bank B
Precharge Command Bank A Activate Command Bank A
Precharge Command Bank B
Write Command Bank A
Integrated Circuit Solution Inc.
DR036-0D 02/04/2005
39
IC42S32200 IC42S32200L
Figure 12.2.Random Row Write (Interleaving Banks) (Burst Length=8,CAS#Latency=2)
T0 T 1 T2
CLK
T3
T4
T5
T6
T7
T8
T9
T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
tCK2
CKE
High
CS#
RAS#
CAS#
WE#
BS0,1
A10
RAx
RBx
RAy
A0-A9
RAx
CAx
RBx
CBx
RAy
CAy
tRCD
DQM
tWR*
tRP
tWR*
DQ
Hi-Z
DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 DBx3 DBx4 DBx5 DBx6 DBx7 DAy0 DAy1 DAy2 DAy3 DAy4
Activate Command Bank A
Write Command Bank A
Activate Command Bank B
Write Command Bank B Precharge Command Bank A
Activate Command Bank A
Write Command Bank A
Precharge Command Bank B
* tWR > tWR(min.)
40
Integrated Circuit Solution Inc.
DR036-0D 02/04/2005
IC42S32200 IC42S32200L
Figure 12.3.Random Row Write (Interleaving Banks) (Burst Length=8,CAS#Latency=3)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK3
CKE High
CS#
RAS#
CAS#
WE#
BS0,1
A10
RAx
RBx
RAy
A0-A9
RAx
CAx
RBx
CBx
RAy
CAy
tRCD
DQM
tWR*
tRP
tWR*
DQ
Hi-Z
DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 DBx3 DBx4 DBx5 DBx6 DBx7 DAy0 DAy1 DAy2 DAy3
Activate Command Bank A
Write Command Bank A
Activate Command Bank B
Write Command Bank B
Precharge Command Bank A
Activate Command Bank A
Write Command Bank A
Precharge Command Bank B
* tWR > tWR(min.)
Integrated Circuit Solution Inc.
DR036-0D 02/04/2005
41
IC42S32200 IC42S32200L
Figure 13.2.Read and Write Cycle (Burst Length=4,CAS#Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
CKE
CS#
RAS#
CAS#
WE#
BS0,1
A10
RAx
A0-A9
RAx
CAx
CAy
CAz
DQM
DQ
Hi-Z
Ax0
Ax1
Ax2
Ax3
DAy0 DAy1
DAy3
Az0
Az1
Az3
Activate Command Bank A
Read Command Bank A
Write Command Bank A
The Write Data is Masked with a Zero Clock Latency
Read Command Bank A
The Read Data is Masked with a Two Clock Latency
42
Integrated Circuit Solution Inc.
DR036-0D 02/04/2005
IC42S32200 IC42S32200L
Figure 13.3.Read and Write Cycle (Burst Length=4,CAS#Latency=3)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK
tCK3
CKE
CS#
RAS#
CAS#
WE#
BS0,1
A10
RAx
A0-A9
RAx
CAx
CAy
CAz
DQM
Hi-Z
DQ
Ax0
Ax1 Ax2
Ax3
DAy0 DAy1
DAy3
Az0
Az1
Az3
Activate Command Bank A
Read Command Bank A
Write The Write Data Command is Masked with a Bank A
Zero Clock Latency
Read Command Bank A
The Read Data is Masked with a Two Clock Latency
Integrated Circuit Solution Inc.
DR036-0D 02/04/2005
43
IC42S32200 IC42S32200L
Figure 14.2.Interleaving Column Read Cycle (Burst Length=4,CAS#Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK
tCK2
CKE
CS#
RAS#
CAS#
WE#
BS0,1
A10
RAx
RAx
A0-A9
RAx
CAy
RAx
CBw
CBx
CBy
CAy
CBz
DQM
tRCD
tAC2
DQ
Hi-Z
Ax0
Ax1
Ax2
Ax3
Bw0 Bw1
Bx0
Bx1
By0
By1
Ay0
Ay1
Bz0 Bz1
Bz2
Bz3
Activate Command Bank A
Read Command Bank A
Activate Command Bank B
Read Command Bank B
Read Command Bank B
Read Command Bank B
Read Command Bank A
Read Command Bank B Precharge Command Bank A
Precharge Command Bank B
44
Integrated Circuit Solution Inc.
DR036-0D 02/04/2005
IC42S32200 IC42S32200L
Figure 14.3.Interleaved Column Read Cycle (Burst Length=4,CAS#Latency=3)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK3
CKE
CS#
RAS#
CAS#
WE#
BS0,1
A10
RAx
RBx
A0-A9
RAx
CAx
RBx
CBx
CBy
CBz
CAy
DQM DQ Hi-Z
tRCD
tAC3
Ax0
Ax1
Ax2
Ax3
Bx0
Bx1
By0
By1
Bz0
Bz1
Ay0
Ay1
Ay2 Ay3
Activate Command Bank A
Read Command Bank A Activate Command Bank B
Read Command Bank B
Read Command Bank B
Read Command Bank B
Read Command Bank A
Precharge Command Bank B
Precharge Command Bank A
Integrated Circuit Solution Inc.
DR036-0D 02/04/2005
45
IC42S32200 IC42S32200L
Figure 15.2.Interleaved Column Write Cycle (Burst Length=4,CAS#Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK
tCK2
CKE
CS#
RAS#
CAS#
WE#
BS0,1
A10
RAx
RBw
A0-A9
RAx
CAx
RBw
CBw
CBx
CBy
CAy
CBz
tRCD
DQM
tRP tRRD
tWR
tRP
DQ
Hi-Z
DAx0 DAx1 DAx2 DAx3 DBw0 DBw1 DBx0 DBx1 DBy0 DBy1 DAy0 DAy1 DBz0 DBz1 DBz2 DBz3
Activate Command Bank A
Write Command Bank A
Activate Command Bank B
Write Command Bank B
Write Command Bank B
Write Command Bank B
Write Command Bank A
Write Command Bank B Precharge Command Bank A
Precharge Command Bank B
46
Integrated Circuit Solution Inc.
DR036-0D 02/04/2005
IC42S32200 IC42S32200L
Figure 15.3.Interleaved Column Write Cycle (Burst Length=4,CAS#Latency=3)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK3
CKE
CS#
RAS#
CAS#
WE#
BS0,1
A10
RAx
RBw
A0-A9
RAx
CAx RBw
CBw
CBx
CBy
CAy
CBz
DQM
tRCD tRRD > tRRD(min)
tWR
tRP
tWR(min)
DQ
Hi-Z
DAx0 DAx1 DAx2 DAx3 DBw0 DBw1 DBx0 DBx1 DBy0 DBy1 DAy0 DAy1 DBz0 DBz1 DBz2 DBz3
Activate Command Bank A
Activate Command Bank B
Write Command Bank B
Write Command Bank B
Write Command Bank B
Write Command Bank A
Write Command Bank A
Write Command Bank B Precharge Command Bank A
Precharge Command Bank B
Integrated Circuit Solution Inc.
DR036-0D 02/04/2005
47
IC42S32200 IC42S32200L
Figure 16.2.Auto Precharge after Read Burst (Burst Length=4,CAS#Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK
tCK2
CKE High
CS#
RAS#
CAS#
WE#
BS0,1
A10
RAx
RBx
RBy
RAz
A0-A9
RAx
CAx
RBx
CBx
RAy
RBy
CBy
RAz
CAz
DQM
Hi-Z
DQ
Ax0
Ax1 Ax2
Ax3
Bx0
Bx1 Bx2
Bx3 Ay0
Ay1
Ay2
Ay3 By0
By1
By2
By3
Az0
Az1
Az2
Activate Command Bank A
Read Command Bank A
Activate Command Bank B
Read with Auto Precharge Command Bank B
Activate Activate Read with Read with Read with Auto Precharge Command Auto Precharge Command Auto Precharge Bank B Bank A Command Command Command Bank B Bank A Bank A
48
Integrated Circuit Solution Inc.
DR036-0D 02/04/2005
IC42S32200 IC42S32200L
Figure 16.3.Auto Precharge after Read Burst (Burst Length=4,CAS#Latency=3)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK
tCK3
CKE High
CS#
RAS#
CAS#
WE#
BS0,1
A10
RAx
RBx
RBy
A0-A9
RAx
CAx
RBx
CBx
CAy
RBy
CBy
DQM
Hi-Z
DQ
Ax0
Ax1
Ax2
Ax3
Bx0
Bx1
Bx2
Bx3 Ay0
Ay1
Ay2
Ay3
By0
By1
By2
By3
Activate Command Bank A
Activate Command Bank B Read Command Bank A
Read with Auto Precharge Command Bank B
Activate Command Bank B
Read with Auto Precharge Command Bank A
Read with Auto Precharge Command Bank B
Integrated Circuit Solution Inc.
DR036-0D 02/04/2005
49
IC42S32200 IC42S32200L
Figure 17.2.Auto Precharge after Write Burst (Burst Length=4,CAS#Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK
tCK2
CKE High CS#
RAS#
CAS#
WE#
BS0,1
A10
RAx
RBx
RBy
RAz
A0-A9
RAx
CAx
RBx
CBx
CAy
RBy
CBy
RAz
CAz
DQM
DQ
Hi-Z
DAx0 DAx1 DAx2 DAx3 DBx0 DBx1 DBx2 DBx3 DAy0 DAy1 DAy2 DAy3
DBy0 DBy1 DBy2 DBy3 DAz0 DAz1 DAz2 DAz3
Activate Command Bank A
Write Command Bank A
Write with Activate Command Auto Precharge Bank B Command
Bank B
Write with Auto Precharge Command Bank A
Write with Write with Activate Activate Command Auto Precharge Command Auto Precharge Bank B Bank A Command Command
Bank B
Bank A
50
Integrated Circuit Solution Inc.
DR036-0D 02/04/2005
IC42S32200 IC42S32200L
Figure 17.3.Auto Precharge after Write Burst (Burst Length=4,CAS#Latency=3)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK3
CKE High
CS#
RAS#
CAS#
WE#
BS0,1
`
A9
RAx
RBx
RBy
A0-A9
RAx
CAx
RBx
CBx
CAy
RBy
CBy
DQM
DQ
Hi-Z
DAx0 DAx1 DAx2 DAx3 DBx0 DBx1 DBx2 DBx3 DAy0 DAy1 DAy2 DAy3
DBy0 DBy1 DBy2 DBy3
Activate Command Bank A
Activate Command Bank B
Write Command Bank A
Write with Auto Precharge Command Bank B
Write with Auto Precharge Command Bank A
Activate Command Bank B
Write with Auto Precharge Command Bank B
Integrated Circuit Solution Inc.
DR036-0D 02/04/2005
51
IC42S32200 IC42S32200L
Figure 18.2.Full Page Read Cycle (Burst Length=Full Page,CAS#Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t CK2
CKE
High
CS#
RAS#
CAS#
WE#
BS0,1
A10
RAx
RBx
RBy
A0-A9
RAx
CAx
RBx
CBx
RBy
DQM
tRP
DQ
Hi-Z
1 Ax Ax+1 Ax+2 Ax-2 AxAx Ax+1 Bx Bx+1 B x+2 Bx+3 Bx+4 Bx+5 Bx+6
Activate Command Bank A
Read Command Bank A
Activate Command Bank B
Read Command Full Page burst operation does not Bank B term in ate when the burst length is sat is fied; the burst counter increments and continues The burst counter wraps bursting beginning with the starting address. from the highest order
Precharge Command Bank B
Activate Command Bank B
page address back to zero during this time interval
Burst Stop Command
52
Integrated Circuit Solution Inc.
DR036-0D 02/04/2005
IC42S32200 IC42S32200L
Figure 18.3.Full Page Read Cycle (Burst Length=Full Page,CAS#Latency=3)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK3
CKE
High
CS#
RAS#
CAS#
WE#
BS0,1
A10
RAx
RBx
RBy
A0-A9
RAx
CAx
RBx
CBx
RBy
DQM
tRP
Hi-Z
DQ
Ax
Ax+1 Ax+2 Ax-2 Ax-1
Ax
Ax+1
Bx
Bx+1 Bx+2 Bx+3 Bx+4 Bx+5
Activate Command Bank A
Read Command Bank A
Activate Command Bank B
satisfied; the burst counter The burst counter wraps increments and continues from the highest order page address back to zero bursting beginning with the starting address. during this time interval
Read Command Full Page burst operation does not Bank B terminate when the burst length is
Precharge Command Bank B
Activate Command Bank B
Burst Stop Command
Integrated Circuit Solution Inc.
DR036-0D 02/04/2005
53
IC42S32200 IC42S32200L
Figure 19.2.Full Page Write Cycle (Burst Length=Full Page,CAS#Latency=2)
T0
CLK
T 1 T2
T3
T4
T5
T6 T7
T8
T9
T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t CK2
CKE
High
CS#
RAS#
CAS#
WE#
BS0,1
A10
RAx
RBx
RBy
A0-A9
RAx
CAx
RBx
CBx
RBy
DQM
DQ
Hi-Z
DAx
DAx+1 DAx+2 DAx+3 DAx-1
DAx
DAx+1 DBx
DBx+1 DBx+2 DBx+3 DBx+4 DBx+55DBx+6
Activate Command Bank A
Write Command Bank A
Activate Command Bank B
Write Command Bank B
Data is ignored
Precharge Command Bank B
Activate Command Bank B
The burst counter wraps from the highest order page address back to zero during this time interval
Full Page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address.
Burst Stop Command
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Integrated Circuit Solution Inc.
DR036-0D 02/04/2005
IC42S32200 IC42S32200L
Figure 19.3.Full Page Write Cycle (Burst Length=Full Page,CAS#Latency=3)
T0
CLK
T 1 T2
T3
T4
T5
T6
T7
T8
T9
T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
tCK3
CKE High CS#
RAS#
CAS#
WE#
BS0,1
A10
RAx
RBx
RBy
A0-A9
RAx
CAx
RBx
CBx
RBy
DQM
Data is ignored
DQ
Hi-Z
DAx
DAx+1 DAx+2 DAx+3 DAx-1 DAx
DAx+1 DBx
DBx+1
DBx+3 DBx+4 DBx+5
Activate Command Bank A
Write Command Bank A
Activate Command Bank B
Write Command Bank B
Precharge Command Bank B
Activate Command Bank B
The burst counter wraps from the highest order page address back to zero during this time interval
Full Page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address.
Burst Stop Command
Integrated Circuit Solution Inc.
DR036-0D 02/04/2005
55
IC42S32200 IC42S32200L
Figure 20.Byte Write Operation (Burst Length=4,CAS#Latency=2)
T0
T 1 T2
T3
T4
T5
T6
T7
T8
T9
T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
CKE High
CS#
RAS#
CAS#
WE#
BS0,1
A10
RAx
A0-A9
RAx
CAx
CAy
CAz
DQM0
DQM1,2,3
DQ0 - DQ7
Ax0
Ax1
Ax2
DAy1 DAy2
Az1
Az2
DQ8 - DQ15
Ax1
Ax2
Ax3
DAy0 DAy1
DAy3
Az1
Az2
Az3
Activate Command Bank A
Read Upper 3 Bytes Command are masked Bank A
Lower Byte is masked
Write Upper 3 Bytes Command are masked Bank A
Read Command Bank A
Lower Byte is masked
Lower Byte is masked
56
Integrated Circuit Solution Inc.
DR036-0D 02/04/2005
IC42S32200 IC42S32200L
Figure 22.Full Page Random Column Read (Burst Length=Full Page,CAS#Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
CKE
CS#
RAS#
CAS#
WE#
BS0,1 A10
RAx
RBx
RBw
A0-A9
RAx
RBx CAx
CBx
CAy
CBy
CAz
CBz
RBw
t RP
DQM
tRRD
DQ
tRCD
Ax0 Bx0 Ay0 Ay1 By0 By1 Az0 Az1 Az2 Bz0 Bz1 Bz2
Activate Command Bank A
Activate Command Bank B
Command Bank B
Read
Command Bank A
Read
Command Bank A
Read
Command Bank B
Read
Command Bank A
Read
Command Bank B
Read
Precharge Command Bank B (Precharge Temination)
Activate Command Bank B
Integrated Circuit Solution Inc.
DR036-0D 02/04/2005
57
IC42S32200 IC42S32200L
Figure 23.Full Page Random Column Write (Burst Length=Full Page,CAS#Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
CKE
CS#
RAS#
CAS#
WE#
BS0,1
A10
RAx
RBx
RBw
A0-A9
RAx
RBx
CAx
CBx
CAy
CBy
CAz
CBz
RBw
t WR
DQM
t RP
tRRD
DQ
t RCD
DAx0 DBx0 DAy0 DAy1 DBy0 DBy1 DAz0 DAz1 DAz2 DBz0 DBz1 DBz2
Activate Command Bank A
Activate Command Bank B
Write Command Bank B Write Write Command Command Bank A Bank A
Write Command Bank B
Write Command Bank A
Write Command Bank B
Precharge Command Bank B (Precharge Temination)
Write Data is masked
Activate Command Bank B
58
Integrated Circuit Solution Inc.
DR036-0D 02/04/2005
IC42S32200 IC42S32200L
Figure 24.2.Precharge Termination of a Burst (Burst Length=8 or Full Page,CAS#Latency=2)
T0
CLK
T 1 T2
T3
T4
T5
T6
T7
T8
T9
T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
tCK2
CKE High CS#
RAS#
CAS#
WE#
BS0,1
A10
RAx
RAy
RAz
A0-A9
RAx
CAx
RAy
CAy
RAz
CAz
tWR tRP
DQM
tRP
tRP
DQ
DAx0 DAx1 DAx2 DAx3
Ay0
Ay1
Ay2
Az0
Az1
Az2
Activate Command Bank A
Write Command Bank A
Precharge Command Bank A
Activate Command Bank A
Command Bank A
Read
Precharge Command Bank A
Precharge Termination of a Write Burst. Write data is masked.
Activate Command Bank A
Command Bank A
Read
Precharge Command Bank A
Precharge Termination of a Read Burst.
Integrated Circuit Solution Inc.
DR036-0D 02/04/2005
59
IC42S32200 IC42S32200L
Figure 24.3.Precharge Termination of a Burst (Burst Length=4,8 or Full Page,CAS#Latency=3)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK3
CKE High
CS#
RAS#
CAS#
WE#
BS0,1
RAx
A10
RAy
RAz
A0-A9
RAx
CAx
RAy
CAy
RAz
t WR
DQM
t RP
tRP
DQ
DAx0 DAx1
Ay0
Ay1
Ay2
Activate Command Bank A
Write Command Bank A
Precharge Command Bank A
Activate Command Bank A
Command Bank A
Read
Precharge Command Bank A
Activate Command Bank A
Precharge Termination of a Read Burst
Write Data is masked
Precharge Termination of a Write Burst
60
Integrated Circuit Solution Inc.
DR036-0D 02/04/2005
IC42S32200 IC42S32200L
ORDERING INFORMATION Commercial Range: 0C to 70C
Frequency 166MHz 166MHz 143MHz 143MHz 125MHz 125MHz Speed (ns) 6 6 7 7 8 8 Order Part No. IC42S32200/L-6T IC42S32200/L-6B IC42S32200/L-7T IC42S32200/L-7B IC42S32200/L-8T IC42S32200/L-8B Package 400mil TSOP-2 11*13mm BGA 400mil TSOP-2 11*13mm BGA 400mil TSOP-2 11*13mm BGA
ORDERING INFORMATION Industrial Temperature Range: -40C to 85C
Frequency 166MHz 166MHz 143MHz 143MHz 125MHz 125MHz Speed (ns) 6 6 7 7 8 8 Order Part No. IC42S32200/L-6TI IC42S32200/L-6BI IC42S32200/L-7TI IC42S32200/L-7BI IC42S32200/L-8TI IC42S32200/L-8BI Package 400mil TSOP-2 11*13mm BGA 400mil TSOP-2 11*13mm BGA 400mil TSOP-2 11*13mm BGA
Integrated Circuit Solution Inc.
DR036-0D 02/04/2005
61
IC42S32200 IC42S32200L
ORDERING INFORMATION (Pb-free Package) Commercial Range: 0C to 70C
Frequency 166MHz 166MHz 143MHz 143MHz 125MHz 125MHz Speed (ns) 6 6 7 7 8 8 Order Part No. IC42S32200/L-6TG IC42S32200/L-6BG IC42S32200/L-7TG IC42S32200/L-7BG IC42S32200/L-8TG IC42S32200/L-8BG Package 400mil TSOP-2 11*13mm BGA 400mil TSOP-2 11*13mm BGA 400mil TSOP-2 11*13mm BGA
ORDERING INFORMATION (Pb-free Package) Industrial Temperature Range: -40C to 85C
Frequency 166MHz 166MHz 143MHz 143MHz 125MHz 125MHz Speed (ns) 6 6 7 7 8 8 Order Part No. IC42S32200/L-6TIG IC42S32200/L-6BIG IC42S32200/L-7TIG IC42S32200/L-7BIG IC42S32200/L-8TIG IC42S32200/L-8BIG Package 400mil TSOP-2 11*13mm BGA 400mil TSOP-2 11*13mm BGA 400mil TSOP-2 11*13mm BGA
Integrated Circuit Solution Inc.
HEADQUARTER: NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK, HSIN-CHU, TAIWAN, R.O.C. TEL: 886-3-5780333 Fax: 886-3-5783000 BRANCH OFFICE: 7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD, HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C. TEL: 886-2-26962140 FAX: 886-2-26962252 http://www.icsi.com.tw
62 Integrated Circuit Solution Inc.
DR036-0D 02/04/2005

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